Semiconductor devices and integrated circuits are becoming more highly integrated. As a result, research is ongoing to improve characteristics of these devices and circuits, and to achieve desirable process margins. Therefore, photolithography processes for forming a pattern over a wafer are important parts of a microlithography process.
In general, interconnect layers are patterned and then etched to form conducting lines. However, at the completion of the etching process, reentrant undercutting has been observed at the interface of the metallic layer and the anti-reflection coating layer, which can lead to undesirable voids during subsequent filling with an inter-metal layer dielectric or, in the worst case, subsequent lifting of the aluminum layer, either of which degrades the yield of semiconductor devices.
This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this Discussion of the Background section constitute prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.